Transition-activity aware design of reduction-stages for parallel multipliers

We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the primary inputs. In typical signal processing applications the transition probability varies between the most and least significant bits. The same is the case for individual signals within the multiplier. Our interconnect reorganization exploits this to reduce the overall switching activity, thus reducing the multiplier’s power consumption. We have developed a CAD tool that reorganizes the connections within the multiplier architecture in an optimized way. Since the applied heuristic requires power estimation, we have also developed a very fast estimator fine tuned for parallel multipliers. The CAD tool automatically generates gate-level VHDL code for the optimized multipliers. This code and code for unoptimized multipliers have been compared using state of the art power estimation tools. The reduction in pow...

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Oscar Gustafsson
• Keywords: GLVLSI 2007, Multiplier’s Power Consumption, Parallel Multiplier, Power Consumption, VLSI