A True Single-Phase 8-bit Adiabatic Multiplier

This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-phase adiabatic logic family. Energy is supplied to the adiabatic circuitry via a sinusoidal power-clock waveform that is generated on-chip. In HSPICE simulations with post-layout extracted parasitics, our design functions correctly at clock frequencies exceeding 200 MHz. The total dissipation of the multiplier core and self-test circuitry approaches 130pJ per operation at 200MHz. Our 11,854-transistor chip has been fabricated in a 0.5 m standard CMOS process with an active area of 0.470mm ? . Correct chip operation has been validated for operating frequencies up to 130MHz, the limit of our experimental setup. Measured dissipation correlates well with HSPICE simulations. Categories and Subject Descriptors B.7.1 [Hardware]: Integrated Circuits--Types and Design Styles; B.8.1 [Hardware]: Performance and Reliabil...

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou
• Keywords: 8-bit Adiabatic Multiplier, DAC 2001, Design Automation, Keywords Adiabatic Logic, Single-phase Adiabatic Logic