Two-level hierarchical register file organization for VLIW processors

High-performance microprocessors are currently designed to exploit the inherent instruction level parallelism (ILP) available in most applications. The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. If more registers than those available in the architecture are required, some actions (such as spill code insertion) have to be applied to reduce this pressure, at the expense of some performance degradation. This degradation could be avoided if a high

• Type: Journal
• Year: 2000
• Where: MICRO
• Authors: Javier Zalamea, Josep Llosa, Eduard Ayguadé, Mateo Valero
• Keywords: Aggressive Scheduling Techniques, Hardware, Instruction Level Parallelism, MICRO 2000, Peak Power Dissipation