Unlocking the design secrets of a 2.29 Gb/s Rijndael processor

This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput at 56 mw of power consumption. We discuss how the high level reference specification in C is translated into a parallel architecture. Design decisions are motivated from a system level viewpoint. The prototyping setup is discussed. Categories and Subject Descriptors C.3 [Special-Purpose and Application-based Systems] General Terms Measurement, Performance, Design, Security. Keywords Rijndael, Encryption, Domain-Specific, Low-Power.

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
• Keywords: Advanced Encryption, Compliant Encryption Chip, DAC 2002, Design Automation, Level Reference Specification