Using an FPGA for Fast Bit Accurate SoC Simulation

In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems were lengthy cycle and bit accurate simulations are required. It is particularly designed for systems that do not fit completely on the simulation platform (i.e. FPGA). As a case study, we use a Network-on-Chip (NoC) that is simulated in SystemC and on the described FPGA simulator. This enables us to observe the NoC behavior under a large variety of traffic patterns. Compared with the SystemC simulation we achieved a factor 80-300 of speed improvement, without compromising the cycle and bit level accuracy.

• Type: Conference
• Year: 2007
• Where: IPPS
• Authors: Pascal T. Wolkotte, Philip K. F. Hölzenspies, Gerard J. M. Smit
• Keywords: Distributed And Parallel Computing, IPPS 2007, Large Parallel Homo, Sequential Simulation Method, Simulation