Extending the transaction level modeling approach for fast communication architecture exploration

System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems. System designers typically use Bus Cycle Accurate (BCA) models written in high level languages such as C/C++ to explore the communication design space. These models capture all of the bus signals and strictly maintain cycle accuracy, which is useful for reliable performance exploration but results in slow simulation speeds for complex designs, even when they are modeled using high level languages. Recently there have been several efforts to use the Transaction Level Modeling (TLM) paradigm for improving simulation performance in BCA models. However these BCA models capture a lot of details that can be eliminated when exploring communication architectures. In this paper we extend the TLM approach and propose a new and ransaction-based modeling abstraction level (CCATB) to the communication design space. Our a...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane
• Keywords: Abstraction Level, BCA Models, Communication Design Space, Computer Architecture, DAC 2004