Value-based bit ordering for energy optimization of on-chip global signal buses

In this paper, we present a technique that exploits the statistical behavior of data values transmitted on global signal buses to determine an energy-efficient ordering of bits that minimizes the inter-wire coupling energy and also reduces total bus energy. Statistics are collected for instruction and data bus traffic from eight SPEC CPU2K benchmarks and an optimization problem is formulated and solved optimally using a publicly-available tool. Results obtained using the optimal bit order on large non-overlapping test samples from the same set of benchmarks show that, on average, adjacent inter-wire coupling energies reduce by about 35.4%

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Krishnan Sundaresan, Nihar R. Mahapatra
• Keywords: DATE 2006, Hardware, Inter-wire Coupling, Inter-wire Coupling Energy, Total Bus Energy