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DATE
2006
IEEE

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Fast-prototyping using the BTnode platform

14 years 5 months ago

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The BTnode platform is a versatile and ﬂexible platform for functional prototyping of ad hoc and sensor networks. Based on an Atmel microcontroller, a Bluetooth radio and a low-...

Jan Beutel

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Id	Views	Title	Status

1	352	Fast-prototyping using the BTnode platform	claim
2	219	Low cost LDPC decoder for DVB-S2	claim
3	202	Automatic systemC design configuration for a faster evaluation of different partitioning alternatives	claim
4	195	Application specific instruction processor based implementation of a GNSS receiver on an FPGA	claim
5	176	Low power synthesis of dynamic logic circuits using fine-grained clock gating	claim
6	173	3dID: a low-power, low-cost hand motion capture device	claim
7	171	4G applications, architectures, design methodology and tools for MPSoC	claim
8	171	Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off	claim
9	159	Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors	claim
10	158	Modeling multiple input switching of CMOS gates in DSM technology using HDMR	claim
11	157	Modeling and simulation of mobile gateways interacting with wireless sensor networks	claim
12	154	An integrated open framework for heterogeneous MPSoC design space exploration	claim
13	153	Analyzing timing uncertainty in mesh-based clock architectures	claim
14	152	Adaptive chip-package thermal analysis for synthesis and design	claim
15	151	Designing MRF based error correcting circuits for memory elements	claim
16	151	40Gbps de-layered silicon protocol engine for TCP record	claim
17	151	An 830mW, 586kbps 1024-bit RSA chip design	claim
18	150	Advanced receiver algorithms for MIMO wireless communications	claim
19	149	Communication architecture optimization: making the shortest path shorter in regular networks-on-chip	claim
20	148	Berger code-based concurrent error detection in asynchronous burst-mode machines	claim
21	147	Quantitative analysis of transaction level models for the AMBA bus	claim
22	145	Building a better Boolean matcher and symmetry detector	claim
23	145	Improved offset-analysis using multiple timing-references	claim
24	143	A coverage metric for the validation of interacting processes	claim
25	142	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits	claim
26	142	Mixed-signal design of a digital input power amplifier for automotive audio applications	claim
27	142	Droplet routing in the synthesis of digital microfluidic biochips	claim
28	141	Evaluating coverage of error detection logic for soft errors using formal methods	claim
29	140	A hybrid framework for design and analysis of fault-tolerant architectures	claim
30	140	Optimization of regular expression pattern matching circuits on FPGA	claim
31	137	Area-efficient error protection for caches	claim
32	136	Defect tolerance of QCA tiles	claim
33	135	FPGA architecture characterization for system level performance analysis	claim
34	134	Power constrained and defect-probability driven SoC test scheduling with test set partitioning	claim
35	134	ASIP-based multiprocessor SoC design for simple and double binary turbo decoding	claim
36	134	Energy efficiency vs. programmability trade-off: architectures and design principles	claim
37	133	Analysis and synthesis of quantum circuits by using quantum decision diagrams	claim
38	133	Automatic generation of operation tables for fast exploration of bypasses in embedded processors	claim
39	132	Energy reduction by workload adaptation in a multi-process environment	claim
40	130	Automatic run-time selection of power policies for operating systems	claim
41	129	Non-gaussian statistical interconnect timing analysis	claim
42	128	Efficient link capacity and QoS design for network-on-chip	claim
43	128	Platform-based design of wireless sensor networks for industrial applications	claim
44	127	Software implementation of Tate pairing over GF(2m)	claim
45	127	ASIP design and synthesis for non linear filtering in image processing	claim
46	127	ASIP architecture for multi-standard wireless terminals	claim
47	127	A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits	claim
48	126	Analysis and modeling of power grid transmission lines	claim
49	126	Communication and co-simulation infrastructure for heterogeneous system integration	claim
50	125	Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)	claim
51	125	Combining simulation and formal methods for system-level performance analysis	claim
52	125	Crosstalk-aware domino logic synthesis	claim
53	125	Formal performance analysis and simulation of UML/SysML models for ESL design	claim
54	124	Timing-driven cell layout de-compaction for yield optimization by critical area minimization	claim
55	124	Cell delay analysis based on rate-of-current change	claim
56	123	Constructing portable compiled instruction-set simulators: an ADL-driven approach	claim
57	123	Networks on chips for high-end consumer-electronics TV system architectures	claim
58	122	Power analysis of mobile 3D graphics	claim
59	121	Analysis of the impact of bus implemented EDCs on on-chip SSN	claim
60	120	Exploiting TLM and object introspection for system-level simulation	claim
61	120	Soft delay error analysis in logic circuits	claim
62	120	Design and test of fixed-point multimedia co-processor for mobile applications	claim
63	120	System-level scheduling on instruction cell based reconfigurable systems	claim
64	120	Battery-aware code partitioning for a text to speech system	claim
65	119	Bootstrapped full--swing CMOS driver for low supply voltage operation	claim
66	119	Performance evaluation for system-on-chip architectures using trace-based transaction level simulation	claim
67	119	Compiler-driven FPGA-area allocation for reconfigurable computing	claim
68	118	New methods and coverage metrics for functional verification	claim
69	118	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit	claim
70	117	Activity clustering for leakage management in SPMs	claim
71	117	Formal verification of systemc designs using a petri-net based representation	claim
72	116	SoC: fuelling the hopes of the mobile industry	claim
73	116	Adaptive data placement in an embedded multiprocessor thread library	claim
74	116	Systematic and optimal design of CMOS two-stage opamps with hybrid cascode compensation	claim
75	115	Application specific NoC design	claim
76	115	Optimal periodic testing of intermittent faults in embedded pipelined processor applications	claim
77	115	Management of complex automotive communication networks	claim
78	114	Associative skew clock routing for difficult instances	claim
79	114	COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC	claim
80	114	An efficient static algorithm for computing the soft error rates of combinational circuits	claim
81	114	A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap	claim
82	114	3D floorplanning with thermal vias	claim
83	114	Compositional, efficient caches for a chip multi-processor	claim
84	113	Automatic ADL-based operand isolation for embedded processors	claim
85	113	An interprocedural code optimization technique for network processors using hardware multi-threading support	claim
86	112	A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs	claim
87	112	Automating processor customisation: optimised memory access and resource sharing	claim
88	112	On the verification of automotive protocols	claim
89	112	Simultaneously improving code size, performance, and energy in embedded processors	claim
90	111	Disclosing the LDPC code decoder design space	claim
91	111	Functional test generation using property decompositions for validation of pipelined processors	claim
92	111	Extraction of defect density and size distributions from wafer sort test results	claim
93	110	Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications	claim
94	110	Online energy-aware I/O device scheduling for hard real-time systems	claim
95	110	Multiprocessor synthesis for periodic hard real-time tasks under a given energy constraint	claim
96	110	Layout driven data communication optimization for high level synthesis	claim
97	110	Top-down heterogeneous synthesis of analog and mixed-signal systems	claim
98	110	An improved RF loopback for test time reduction	claim
99	109	A secure scan design methodology	claim
100	109	A methodology for mapping multiple use-cases onto networks on chips	claim
101	109	A single photon avalanche diode array fabricated in deep-submicron CMOS technology	claim
102	108	Automatic march tests generations for static linked faults in SRAMs	claim
103	108	Scheduling under resource constraints using dis-equations	claim
104	108	Lens aberration aware timing-driven placement	claim
105	108	Software-friendly HW/SW co-simulation: an industrial case study	claim
106	108	Test compaction for transition faults under transparent-scan	claim
107	108	Architectural and technology influence on the optimal total power consumption	claim
108	108	Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults	claim
109	107	Flexible specification and application of rule-based transformations in an automotive design flow	claim
110	107	Disjunctive image computation for embedded software verification	claim
111	107	Time domain model order reduction by wavelet collocation method	claim
112	106	Architectures for efficient face authentication in embedded systems	claim
113	106	Memory centric thread synchronization on platform FPGAs	claim
114	105	Optical routing for 3D system-on-package	claim
115	105	Comfortable modeling of complex reactive systems	claim
116	105	Statistical timing analysis with path reconvergence and spatial correlations	claim
117	104	Contrasting a NoC and a traditional interconnect fabric with layout awareness	claim
118	104	Pre-synthesis optimization of multiplications to improve circuit performance	claim
119	104	Equivalence verification of arithmetic datapaths with multiple word-length operands	claim
120	104	Optimizing sequential cycles through Shannon decomposition and retiming	claim
121	104	Integrated placement and skew optimization for rotary clocking	claim
122	103	Novel designs for thermally robust coplanar crossing in QCA	claim
123	102	Faster exploration of high level design alternatives using UML for better partitions	claim
124	102	Pseudorandom functional BIST for linear and nonlinear MEMS	claim
125	102	A systematic IP and bus subsystem modeling for platform-based system design	claim
126	101	On the numerical verification of probabilistic rewriting systems	claim
127	101	Classification trees for random tests and functional coverage	claim
128	101	Cooptimization of interface hardware and software for I/O controllers	claim
129	101	A parallel configuration model for reducing the run-time reconfiguration overhead	claim
130	101	Design with race-free hardware semantics	claim
131	101	On-chip bus thermal analysis and optimization	claim
132	100	Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh	claim
133	100	Heterogeneous behavioral hierarchy for system level designs	claim
134	99	Parallel co-simulation using virtual synchronization with redundant host execution	claim
135	99	Multiple-fault diagnosis based on single-fault activation and single-output observation	claim
136	98	Test generation for combinational quantum cellular automata (QCA) circuits	claim
137	98	Power-constrained test scheduling for multi-clock domain SoCs	claim
138	97	Diagnosis of defects on scan enable and clock trees	claim
139	97	Monolithic verification of deep pipelines with collapsed flushing	claim
140	96	On the relation between simulation-based and SAT-based diagnosis	claim
141	96	A methodology for FPGA to structured-ASIC synthesis and verification	claim
142	96	Multi-sensor configurable platform for automotive applications	claim
143	95	An effective technique for minimizing the cost of processor software-based diagnosis in SoCs	claim
144	95	Two-phase resonant clocking for ultra-low-power hearing aid applications	claim
145	95	Efficient AC analysis of oscillators using least-squares methods	claim
146	95	Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications	claim
147	95	Satisfiability-based framework for enabling side-channel attacks on cryptographic software	claim
148	94	The ultra low-power wiseNET system	claim
149	94	An analytical state dependent leakage power model for FPGAs	claim
150	94	Reuse-based test access and integrated test scheduling for network-on-chip	claim
151	94	Procrastinating voltage scheduling with discrete frequency sets	claim
152	94	Sociology of design and EDA	claim
153	94	An integrated scratch-pad allocator for affine and non-affine code	claim
154	94	Large power grid analysis using domain decomposition	claim
155	93	Software annotations for power optimization on mobile devices	claim
156	93	Restructuring field layouts for embedded memory systems	claim
157	92	Space-efficient FPGA-accelerated collision detection for virtual prototyping	claim
158	92	Priority scheduling in digital microfluidics-based biochips	claim
159	91	On-chip 8GHz non-periodic high-swing noise detector	claim
160	91	Avoiding false negatives in formal verification for protocol-driven blocks	claim
161	91	Virtual prototyping of embedded platforms for wireless and multimedia	claim
162	91	Is "Network" the next "Big Idea" in design?	claim
163	91	A dynamically reconfigurable packet-switched network-on-chip	claim
164	91	Customization of application specific heterogeneous multi-pipeline processors	claim
165	91	How OEMs and suppliers can face the network integration challenges	claim
166	91	Dynamic partitioning of processing and memory resources in embedded MPSoC architectures	claim
167	91	Efficient incremental clock latency scheduling for large circuits	claim
168	90	Automatic identification of application-specific functional units with architecturally visible storage	claim
169	90	Efficient design space exploration of high performance embedded out-of-order processors	claim
170	90	Microarchitectural floorplanning under performance and thermal tradeoff	claim
171	90	A time predictable Java processor	claim
172	90	Efficient unknown blocking using LFSR reseeding	claim
173	89	A practical method to estimate interconnect responses to variabilities	claim
174	89	Model-based development of in-vehicle software	claim
175	89	Buffer space optimisation with communication synthesis and traffic shaping for NoCs	claim
176	89	Generation of broadside transition fault test sets that detect four-way bridging faults	claim
177	89	Automatic insertion of low power annotations in RTL for pipelined microprocessors	claim
178	88	Enabling fine-grain leakage management by voltage anchor insertion	claim
179	88	Using conjugate symmetries to enhance gate-level simulations	claim
180	88	Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures	claim
181	88	Timing-reasoning-based delay fault diagnosis	claim
182	87	Supporting task migration in multi-processor systems-on-chip: a feasibility study	claim
183	87	A mixed-signal verification kit for verification of analogue-digital circuits	claim
184	87	Thermal resilient bounded-skew clock tree optimization methodology	claim
185	86	Synthesis of system verilog assertions	claim
186	86	MATLAB/Simulink for automotive systems design	claim
187	86	Hierarchy-aware and area-efficient test infrastructure design for core-based system chips	claim
188	85	A synthesis tool for power-efficient base-band filter design	claim
189	85	Optimizing high speed arithmetic circuits using three-term extraction	claim
190	85	Strong conflict analysis for propositional satisfiability	claim
191	85	Distance-guided hybrid verification with GUIDO	claim
192	85	Test set enrichment using a probabilistic fault model and the theory of output deviations	claim
193	84	Vulnerability analysis of L2 cache elements to single event upsets	claim
194	84	Efficient test-data compression for IP cores using multilevel Huffman coding	claim
195	84	Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses	claim
196	84	Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology	claim
197	83	Dynamic scratch-pad memory management for irregular array access patterns	claim
198	83	What lies between design intent coverage and model checking?	claim
199	82	Efficient assertion based verification using TLM	claim
200	82	Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities	claim
201	82	Dynamic code overlay of SDF-modeled programs on low-end embedded systems	claim
202	82	Value-based bit ordering for energy optimization of on-chip global signal buses	claim
203	82	Systematic stability-analysis method for analog circuits	claim
204	82	Performance analysis of greedy shapers in real-time systems	claim
205	82	Concurrent core test for SOC using shared test set and scan chain disable	claim
206	81	Lock-free synchronization for dynamic embedded real-time systems	claim
207	81	Efficient factorization of DSP transforms using taylor expansion diagrams	claim
208	80	Coverage loss by using space compactors in presence of unknown values	claim
209	80	Energy-efficient FPGA interconnect design	claim
210	80	Software-based self-test of processors under power constraints	claim
211	78	Wireless sensor networks and beyond	claim
212	78	STAX: statistical crosstalk target set compaction	claim
213	78	Functional constraints vs. test compression in scan-based delay testing	claim
214	78	A time-triggered ethernet (TTE) switch	claim
215	77	Soft-error classification and impact analysis on real-time operating systems	claim
216	77	Proven correct monitors from PSL specifications	claim
217	76	Efficient minimization of fully testable 2-SPP networks	claim
218	76	Performance optimization for energy-aware adaptive checkpointing in embedded real-time systems	claim
219	75	Space of DRAM fault models and corresponding testing	claim
220	75	GALS networks on chip: a new solution for asynchronous delay-insensitive links	claim
221	74	Hardware efficient architectures for Eigenvalue computation	claim
222	73	Minimizing test power in SRAM through reduction of pre-charge activity	claim
223	73	Verifying analog oscillator circuits using forward/backward abstraction refinement	claim
224	73	Double-sampling single-loop sigma-delta modulator topologies for broadband applications	claim
225	72	HDL models of ferromagnetic core hysteresis using timeless discretisation of the magnetic slope	claim
226	72	An ultra low-power TLB design	claim
227	72	A design for failure analysis (DFFA) technique to ensure incorruptible signatures	claim
228	71	Quantifier structure in search based procedures for QBFs	claim
229	71	Exploring "temperature-aware" design in low-power MPSoCs	claim
230	71	A logarithmic full-chip thermal analysis algorithm based on multi-layer Green's function	claim
231	70	A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures	claim
232	70	A low complexity heuristic for design of custom network-on-chip architectures	claim
233	69	A new approach to compress the configuration information of programmable devices	claim
234	68	Functional verification methodology based on formal interface specification and transactor generation	claim
235	66	On test conditions for the detection of open defects	claim
236	66	Power/performance hardware optimization for synchronization intensive applications in MPSoCs	claim
237	65	RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics	claim
238	64	Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms	claim
239	50	Task-accurate performance modeling in SystemC for real-time multi-processor architectures	claim

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