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FTCS
1997

VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions

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VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
Volkmar Sieh, Oliver Tschäche, Frank Balbach
Added 01 Nov 2010
Updated 01 Nov 2010
Type Conference
Year 1997
Where FTCS
Authors Volkmar Sieh, Oliver Tschäche, Frank Balbach
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