Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip

Abstract— Three-dimensional (3D) integration and Networkon-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs’ utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant T...

• Type: Journal
• Year: 2011
• Where: ASPDAC
• Authors: Cheng Liu, Lei Zhang 0008, Yinhe Han, Xiaowei Li
• Keywords: 3d Mesh, ASPDAC 2011, Design Challenges, Hardware, Time Division Multiplex