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IWSOC
2005
IEEE

Very High Radix Scalable Montgomery Multipliers

14 years 5 months ago
Very High Radix Scalable Montgomery Multipliers
This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Koç scalable architecture using w × v – bit integer multipliers in place of AND gates. The new design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 x 16 multipliers, making it the fastest scalable design yet reported.
Kyle Kelley, David Harris
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where IWSOC
Authors Kyle Kelley, David Harris
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