VHDL-based communication and synchronization synthesis

This paper describes an approach for VHDL-based communication and synchronization synthesis. This design step transforms a system level VHDL description into an RT-level description. The idea is, not to synthesize system level implementations of communication and synchronization mechanisms but to perform hesis step as a mapping step of an abstract communication or synchronization mechanism to one of a set of RT-level implementations. The major sub-problem, which needed to be solved for the synthesis algorithm was the topology dependent mapping of implementations.

• Type: Conference
• Year: 1995
• Where: EURODAC
• Authors: Wolfgang Ecker, Manfred Huber
• Keywords: EURODAC 1995, Level Vhdl Description, Synchronization Mechanism, Synchronization Synthesis, VHDL