VHDL extensions for complex transmission line simulation

This paper proposes extensions to the VHDL grammar and denes new semantics in the language to model the timing behavior of high frequency buses and clock lines with multiple, distinct taps in a VHDL description. The proposed language constructs utilize transmission line analysis to model the timing behavior but avoids the continuous time simulation by using lineevents.

• Type: Conference
• Year: 1997
• Where: DATE
• Authors: Peter Walker, Sumit Ghosh
• Keywords: DATE 1997, Hardware, Paper Proposes Extensions, Timing Behavior, VHDL Grammar