A VLSI Implementation of a Cascade Viterbi Decoder with Traceback

- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read pointer traceback technique. The overall design for a 16-qtate, rate 1/2 decoder requires about 26000 transistors and a core area of 8.5

• Type: Conference
• Year: 1993
• Where: ISCAS
• Authors: Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton
• Keywords: Hardware, ISCAS 1993, Rate 1/2 Decoder, Single Read Pointer, Survivor Sequence Memory