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23
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ISCAS
1993
IEEE
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ISCAS 1993
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A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
14 years 3 months ago
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www.eecg.toronto.edu
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Ch...
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