What lies between design intent coverage and model checking?

Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that can be checked on the sub-modules of the parent module. To support this methodology, we have developed a formal methodology for verifying whether the decomposition is indeed sound and complete, that is, whether verifying the smaller properties on the submodules actually guarantees the original property on the parent module. In practice, however designers do not write properties for all modules and thereby our previous methodology was applicable to selected cases only. In this paper we present new formal methods that allow us to handle RTL blocks in the analysis. We believe that the new approach will significantly widen the scope of the methodology, thereby enabling the validation engineer to handle much larger designs than admitted by existing formal verification tools.

• Type: Conference
• Year: 2006
• Where: DATE
• Authors: Sayantan Das, Prasenjit Basu, Pallab Dasgupta, P. P. Chakrabarti
• Keywords: DATE 2006, Formal Verification Tools, Hardware, Parent Module, Smaller Properties