On whitespace and stability in physical synthesis

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits as well as the increasing use of buffered interconnect. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic re-synthesis targeting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool. In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces pl...

• Type: Journal
• Year: 2006
• Where: INTEGRATION
• Authors: Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
• Keywords: INTEGRATION 2006, Large-scale Standard-cell Placement, Physical Synthesis, Placement Require