INTEGRATION
2008
13 years 11 months ago
2008
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
INTEGRATION
2006
14 years 22 days ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
INTEGRATION
2006
14 years 22 days ago
2006
INTEGRATION
2006
14 years 22 days ago
2006
INTEGRATION
2006
14 years 22 days ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...