Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects

This paper presents a wrapper and TAM co-optimization method for reuse of SoC functional interconnects to minimize test time under area constraint. The proposed method consists of (1) an ILP formulation for wrapper and transparent TAM cooptimization, and (2) a simulated annealing based heuristic approach to reduce the computational cost of the proposed ILP model. Experimental results show the effectiveness of the proposed methods compared to the previous transparency-based TAM approaches and the conventional dedicated test bus approaches.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Tomokazu Yoneda, Hideo Fujiwara
• Keywords: DATE 2008, Hardware, TAM Co-optimization Method, Transparency-based Tam Approaches, Transparent Tam Cooptimization