A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264

—This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of CAVLC decoding process to efficient skip possible processes if none needed to be decoded, and can decode multiple symbols in sign and run before stage. The proposed design just needs average 90 cycles for one MB decoding, which can meet real time HDTV requirement and saves 64% of cycle count in average when compared with previous design. The hardware cost is about 13192 gates when synthesized at 125 MHz.

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Guo-Shiuan Yu, Tian-Sheuan Chang
• Keywords: Average 90 Cycles, CAVLC Decoding Process, Cavlc Decoding Vlsi, ISCAS 2006