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DAC
2005
ACM
14 years 10 months ago
Low power network processor design using clock gating
Abstract-- Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers. Typical NPs incorporate mu...
Jia Yu, Jun Yang 0002, Laxmi N. Bhuyan, Yan Luo
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 3 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
CRIWG
2007
13 years 10 months ago
Deployment of Ontologies for an Effective Design of Collaborative Learning Scenarios
Two of the most important research subjects during the development of intelligent authoring systems (IAS) for education are the modeling of knowledge and the extraction of knowledg...
Seiji Isotani, Riichiro Mizoguchi
HICSS
2007
IEEE
170views Biometrics» more  HICSS 2007»
14 years 3 months ago
Articulation Work Supporting Information Infrastructure Design: Coordination, Categorization, and Assessment in Practice
Articulation work is a critical factor in information infrastructure building projects that involve multiple and diverse communities. It brings awareness of language differences, ...
Karen S. Baker, Florence Millerand
WDAG
2007
Springer
102views Algorithms» more  WDAG 2007»
14 years 3 months ago
A Denial-of-Service Resistant DHT
We consider the problem of designing scalable and robust information systems based on multiple servers that can survive even massive denial-of-service (DoS) attacks. More precisely...
Baruch Awerbuch, Christian Scheideler