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» : Designing a Scalable Build Process
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IPPS
1999
IEEE
13 years 12 months ago
Scalable Hardware-Algorithms for Binary Prefix Sums
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
14 years 4 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 1 months ago
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Buildi
As the logic capacity of FPGA increases, there has been a corresponding increase in the variety of FPGA building blocks. From a mere collection of the conventional logic blocks, F...
Andy Gean Ye, Jonathan Rose
ER
2004
Springer
93views Database» more  ER 2004»
14 years 1 months ago
A Pattern and Dependency Based Approach to the Design of Process Models
Abstract. In this paper an approach for building process models for ecommerce is proposed. It is based on the assumption that the process modeling task can be methodologically supp...
Maria Bergholtz, Prasad Jayaweera, Paul Johannesso...
BPM
2006
Springer
119views Business» more  BPM 2006»
13 years 11 months ago
Business Process Design by View Integration
Even though the design of business processes most often has to consolidate the knowledge of several process stakeholders, this fact is utilized only to a limited extent by existing...
Jan Mendling, Carlo Simon