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FPGA
1997
ACM
124views FPGA» more  FPGA 1997»
13 years 11 months ago
YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing
This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a network contr...
Akihiro Tsutsui, Toshiaki Miyazaki
ICDM
2010
IEEE
276views Data Mining» more  ICDM 2010»
13 years 4 months ago
Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs
Many time series data mining problems require subsequence similarity search as a subroutine. While this can be performed with any distance measure, and dozens of distance measures ...
Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamon...
ICCAD
2003
IEEE
194views Hardware» more  ICCAD 2003»
14 years 3 months ago
On the Interaction Between Power-Aware FPGA CAD Algorithms
As Field-Programmable Gate Array (FPGA) power consumption continues to increase, lower power FPGA circuitry, architectures, and Computer-Aided Design (CAD) tools need to be develo...
Julien Lamoureux, Steven J. E. Wilton
IJCNN
2000
IEEE
13 years 11 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa
BMCBI
2010
109views more  BMCBI 2010»
13 years 7 months ago
FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Background: Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data. Th...
Stephanie Zierke, Jason D. Bakos