ICCAD 2003 - PDF Preprint Papers

ICCAD 2003 International Conference on Computer-Aided Design

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ICCAD
2003
IEEE

379views Hardware» more ICCAD 2003»

A Statistical Gate-Delay Model Considering Intra-Gate Variability

14 years 8 months ago

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This paper proposes a model for calculating statistical gate-delay variation caused by intra-chip and inter-chip variability. As the variation of individual gate delays directly i...

Ken-ichi Okada, Kento Yamaoka, Hidetoshi Onodera

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Id	Views	Title	Status

1	379	A Statistical Gate-Delay Model Considering Intra-Gate Variability	claim
2	325	Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading	claim
3	221	Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems	claim
4	219	A Min-Cost Flow Based Detailed Router for FPGAs	claim
5	210	Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems	claim
6	205	Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations	claim
7	204	Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation	claim
8	198	A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits	claim
9	195	Compiler-Based Register Name Adjustment for Low-Power Embedded Processors	claim
10	195	Vectorless Analysis of Supply Noise Induced Delay Variation	claim
11	194	On the Interaction Between Power-Aware FPGA CAD Algorithms	claim
12	193	FROSTY: A Fast Hierarchy Extractor for Industrial CMOS Circuits	claim
13	190	IDAP: A Tool for High Level Power Estimation of Custom Array Structures	claim
14	188	Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization	claim
15	175	Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication	claim
16	175	Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis	claim
17	170	Evaluation of Placement Techniques for DNA Probe Array Layout
18	166	Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems	claim
19	161	A General S-Domain Hierarchical Network Reduction Algorithm	claim
20	159	Array Composition and Decomposition for Optimizing Embedded Applications	claim
21	159	Energy-Aware Fault Tolerance in Fixed-Priority Real-Time Embedded Systems	claim
22	159	Mixed Signal DFT: A Concise Overview	claim
23	158	Approaching the Maximum Energy Saving on Embedded Systems with Multiple Voltages	claim
24	156	Dynamic Data-bit Memory Built-In Self- Repair	claim
25	154	Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs	claim
26	154	Length-Matching Routing for High-Speed Printed Circuit Boards	claim
27	152	Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches	claim
28	152	Fredkin/Toffoli Templates for Reversible Logic Synthesis	claim
29	152	Binding, Allocation and Floorplanning in Low Power High-Level Synthesis	claim
30	152	Dynamic Fault-Tolerance and Metrics for Battery Powered, Failure-Prone Systems	claim
31	152	Efficient Iterative Time Preconditioners for Harmonic Balance RF Circuit Simulation	claim
32	152	An Algorithmic Approach for Generic Parallel Adders	claim
33	151	On Compacting Test Response Data Containing Unknown Values	claim
34	149	Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level	claim
35	148	Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization	claim
36	148	The Compositional Far Side of Image Computation	claim
37	147	A Fast Crosstalk- and Performance-Driven Multilevel Routing System	claim
38	145	Manufacturing-Aware Physical Design	claim
39	144	A High-level Interconnect Power Model for Design Space Exploration	claim
40	143	Fractional Cut: Improved Recursive Bisection Placement	claim
41	142	SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation	claim
42	142	Energy Optimization of Distributed Embedded Processors by Combined Data Compression and Functional Partitioning	claim
43	141	Passive Synthesis of Compact Frequency-Dependent Interconnect Models via Quadrature Spectral Rules	claim
44	141	An Enhanced Multilevel Algorithm for Circuit Placement	claim
45	140	Block-based Static Timing Analysis with Uncertainty	claim
46	140	Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation	claim
47	140	Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics	claim
48	139	Equivalent Waveform Propagation for Static Timing Analysis	claim
49	138	Multi-Million Gate FPGA Physical Design Challenges	claim
50	137	Bus-Driven Floorplanning	claim
51	136	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications	claim
52	136	Adjustable Width Linear Combinational Scan Vector Decompression	claim
53	135	ATPG for Noise-Induced Switch Failures in Domino Logic	claim
54	134	A Game Theoretic Approach to Dynamic Energy Minimization in Wireless Transceivers	claim
55	134	Multi-Domain Clock Skew Scheduling	claim
56	132	A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines	claim
57	131	LRU-SEQ: A Novel Replacement Policy for Transition Energy Reduction in Instruction Caches	claim
58	131	A New Surface Integral Formulation For Wideband Impedance Extraction of 3-D Structures	claim
59	130	Analog Macromodeling using Kernel Methods	claim
60	129	ILP Models for the Synthesis of Asynchronous Control Circuits	claim
61	129	SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips	claim
62	129	Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels	claim
63	127	A Probabilistic-Based Design Methodology for Nanoscale Computation	claim
64	127	Performance Efficiency of Context-Flow System-on-Chip Platform	claim
65	127	Layout-Aware Scan Chain Synthesis for Improved Path Delay Fault Coverage	claim
66	127	Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design	claim
67	124	A Statistical Approach to Estimate the Dynamic Non-Linearity Parameters of Pipeline ADCs	claim
68	124	A Generalized Method for Computing Oscillator Phase Noise Spectra	claim
69	124	Gradual Relaxation Techniques with Applications to Behavioral Synthesis	claim
70	123	The Y-Architecture for On-Chip Interconnect: Analysis and Methodology	claim
71	123	A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits	claim
72	123	Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion	claim
73	122	Weibull Based Analytical Waveform Model	claim
74	122	Efficient Generation of Monitor Circuits for GSTE Assertion Graphs	claim
75	122	A Framework for Designing Reusable Analog Circuits	claim
76	120	RTL Power Optimization with Gate-Level Accuracy	claim
77	119	Analytical Bound for Unwanted Clock Skew due to Wire Width Variation	claim
78	119	Dynamic Platform Management for Configurable Platform-Based System-on-Chips	claim
79	118	Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach	claim
80	117	On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis	claim
81	115	SOI Transistor Model for Fast Transient Simulation	claim
82	115	Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits	claim
83	114	A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning	claim
84	113	Retiming with Interconnect and Gate Delay	claim
85	113	Branch Merge Reduction of RLCM Networks	claim
86	111	Simultaneous Analytic Area and Power Optimization for Repeater Insertion	claim
87	111	Formal Methods for Dynamic Power Management	claim
88	111	A Trade-off Oriented Placement Tool	claim
89	110	Optimality and Stability Study of Timing-Driven Placement Algorithms	claim
90	109	Large-Scale Circuit Placement: Gap and Promise	claim
91	105	TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers	claim
92	103	Static Verification of Test Vectors for IR Drop Failure	claim
93	100	A Theory of Non-Deterministic Networks	claim
94	99	A Probabilistic Approach to Buffer Insertion	claim
95	98	Achieving Design Closure Through Delay Relaxation Parameter	claim
96	97	Iterative Abstraction using SAT-based BMC with Proof Analysis	claim

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