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CASES
2004
ACM
14 years 24 days ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
APCSAC
2001
IEEE
13 years 11 months ago
Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading
Java bytecodes can be executed with the following three methods: a Java interpretor running on a particular machine interprets bytecodes; a Just-In-Time (JIT) compiler translates ...
Kenji Watanabe, Wanming Chu, Yamin Li
SIGMOD
2004
ACM
166views Database» more  SIGMOD 2004»
14 years 7 months ago
Fast Computation of Database Operations using Graphics Processors
We present new algorithms on commodity graphics processors to perform fast computation of several common database operations. Specifically, we consider operations such as conjunct...
Naga K. Govindaraju, Brandon Lloyd, Wei Wang 0010,...
CASES
2010
ACM
13 years 5 months ago
Fine-grain dynamic instruction placement for L0 scratch-pad memory
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
JongSoo Park, James D. Balfour, William J. Dally
LCPC
2000
Springer
13 years 11 months ago
Efficient Dynamic Local Enumeration for HPF
In translating HPF programs, a compiler has to generate local iteration and communication sets. Apart from local enumeration, local storage compression is an issue, because in HPF ...
Will Denissen, Henk J. Sips