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MICRO
1995
IEEE
72views Hardware» more  MICRO 1995»
14 years 1 months ago
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures
Lack of object code compatibility in VLIW architectures is a severe limit to their adoption as a generalpurpose computing paradigm. Previous approaches include hardware and softwa...
Thomas M. Conte, Sumedh W. Sathaye
CGO
2010
IEEE
14 years 4 months ago
Automated just-in-time compiler tuning
Managed runtime systems, such as a Java virtual machine (JVM), are complex pieces of software with many interacting components. The Just-In-Time (JIT) compiler is at the core of t...
Kenneth Hoste, Andy Georges, Lieven Eeckhout
HPCA
1997
IEEE
14 years 2 months ago
Architectural Support for Compiler-Synthesized Dynamic Branch Prediction Strategies: Rationale and Initial Results
This paper introduces a new architectural approach that supports compiler-synthesized dynamic branch predication. In compiler-synthesized dynamic branch prediction, the compiler g...
David I. August, Daniel A. Connors, John C. Gyllen...
DELTA
2010
IEEE
14 years 3 months ago
Algorithm Transformation for FPGA Implementation
— High level hardware description languages aim to make hardware design more like programming software. These languages are often used to accelerate legacy software algorithms by ...
Donald G. Bailey, Christopher T. Johnston
ENTCS
2002
78views more  ENTCS 2002»
13 years 9 months ago
ESUIF: An Open Esterel Compiler
I describe a new compiler infrastructure for imperative synchronous languages such as Esterel and ecl. Built on the suif 2 system, it includes a new intermediate representation fo...
Stephen Edwards