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» A C to Hardware Software Compiler
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TC
2010
13 years 4 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch
FPL
2007
Springer
105views Hardware» more  FPL 2007»
14 years 4 months ago
An Execution Model for Hardware/Software Compilation and its System-Level Realization
We introduce a new execution model for orchestrating the interaction between the conventional processor and the reconfigurable compute unit in adaptive computer systems. We then ...
Holger Lange, Andreas Koch
CASES
2006
ACM
14 years 3 months ago
Automatic performance model construction for the fast software exploration of new hardware designs
Developing an optimizing compiler for a newly proposed architecture is extremely difficult when there is only a simulator of the machine available. Designing such a compiler requ...
John Cavazos, Christophe Dubach, Felix V. Agakov, ...
ICCAD
2007
IEEE
101views Hardware» more  ICCAD 2007»
14 years 6 months ago
A novel SoC design methodology combining adaptive software and reconfigurable hardware
Marco D. Santambrogio, Seda Ogrenci Memik, Vincenz...
CC
2008
Springer
240views System Software» more  CC 2008»
13 years 11 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David