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IEEEPACT
2000
IEEE
15 years 10 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
INFOVIS
2000
IEEE
15 years 10 months ago
Visualizing Massive Multi-Digraphs
We describe MGV, an integrated visualization and exploration system for massive multi-digraph navigation. MGV’s only assumption is that the vertex set of the underlying digraph ...
James Abello, Jeffrey L. Korn
VTS
2000
IEEE
99views Hardware» more  VTS 2000»
15 years 10 months ago
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
Abhijit Jas, Bahram Pouya, Nur A. Touba
CVPR
2010
IEEE
15 years 10 months ago
Refinement of Digital Elevation Models from Shadowing Cues
In this paper we derive formal constraints relating terrain elevation and observed cast shadows. We show how an optimisation framework can be used to refine surface estimates usin...
James Hogan, William Smith
CIKM
2000
Springer
15 years 10 months ago
Object and Query Transformation: Supporting Multi-Dimensional Queries through Code Reuse
The complexity of deploying high-performance spatial structures in transactional DBMS environments has motivated researchers to experiment with the idea of reusing the effort inve...
Ratko Orlandic, Byunggu Yu