Sciweavers

1729 search results - page 302 / 346
» A Case-Based Parallel Programming System
Sort
View
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 2 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
OOPSLA
2009
Springer
14 years 2 months ago
A concurrent dynamic analysis framework for multicore hardware
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
Jungwoo Ha, Matthew Arnold, Stephen M. Blackburn, ...
IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick
ICPP
2003
IEEE
14 years 28 days ago
Data Conversion for Process/Thread Migration and Checkpointing
Process/thread migration and checkpointing schemes support load balancing, load sharing and fault tolerance to improve application performance and system resource usage on worksta...
Hai Jiang, Vipin Chaudhary, John Paul Walters
CORR
2010
Springer
128views Education» more  CORR 2010»
13 years 7 months ago
A Performance Study of GA and LSH in Multiprocessor Job Scheduling
Multiprocessor task scheduling is an important and computationally difficult problem. This paper proposes a comparison study of genetic algorithm and list scheduling algorithm. Bo...
S. R. Vijayalakshmi, G. Padmavathi