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» A Clustered Approach to Multithreaded Processors
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IPPS
2009
IEEE
14 years 2 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
IPPS
2006
IEEE
14 years 1 months ago
Detecting phases in parallel applications on shared memory architectures
Most programs are repetitive, where similar behavior can be seen at different execution times. Algorithms have been proposed that automatically group similar portions of a program...
Erez Perelman, Marzia Polito, Jean-Yves Bouguet, J...
IPPS
2005
IEEE
14 years 1 months ago
High-Performance Direct Pairwise Comparison of Large Genomic Sequences
Many applications in Comparative Genomics lend themselves to implementations that take advantage of common high-performance features in modern microprocessors. However, the common...
Christopher Mueller, Mehmet M. Dalkilic, Andrew Lu...
ICPP
2002
IEEE
14 years 15 days ago
Out-of-Order Instruction Fetch Using Multiple Sequencers
Conventional instruction fetch mechanisms fetch contiguous blocks of instructions in each cycle. They are difficult to scale since taken branches make it hard to increase the siz...
Paramjit S. Oberoi, Gurindar S. Sohi
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
14 years 14 days ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita