9 search results - page 1 / 2 » A Coarse-Grained FPGA Architecture for High-Performance FIR ... |
FPGA
1998
ACM
13 years 11 months ago
1998
ACM
ARC
2006
Springer
13 years 11 months ago
2006
Springer
This paper presents a reconfigurable hardware architecture for Public-key cryptosystems. By changing the connections of coarse grain Carry-Save Adders (CSAs), the datapath provides...
FPGA
2004
ACM
14 years 22 days ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
ISCAS
1993
IEEE
13 years 11 months ago
1993
IEEE
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...