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IPPS
2002
IEEE
15 years 8 months ago
Efficient Pipelining of Nested Loops: Unroll-and-Squash
The size and complexity of current custom VLSI have forced the use of high-level programming languages to describe hardware, and compiler and synthesis technology bstract designs ...
Darin Petkov, Randolph E. Harr, Saman P. Amarasing...
134
Voted
HPCA
1995
IEEE
15 years 7 months ago
Software Cache Coherence for Large Scale Multiprocessors
Shared memory is an appealing abstraction for parallel programming. It must be implemented with caches in order toperform well, however, and caches require a coherence mechanism t...
Leonidas I. Kontothanassis, Michael L. Scott
142
Voted
CLOUDCOM
2010
Springer
15 years 1 months ago
Performance Analysis of High Performance Computing Applications on the Amazon Web Services Cloud
Cloud computing has seen tremendous growth, particularly for commercial web applications. The on-demand, pay-as-you-go model creates a flexible and cost-effective means to access c...
Keith R. Jackson, Lavanya Ramakrishnan, Krishna Mu...
140
Voted
IPPS
1998
IEEE
15 years 8 months ago
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors
In this paper, the effect of switch design on the application performance of cache-coherent non-uniform memory access (CC-NUMA) multiprocessors is studied in detail. Wormhole rout...
Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhile...
110
Voted
APPT
2009
Springer
15 years 7 months ago
Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs
Abstract. In many-core CMP architectures, the cache coherence protocol is a key component since it can add requirements of area and power consumption to the final design and, there...
Alberto Ros, Manuel E. Acacio, José M. Garc...