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VEE
2010
ACM
327views Virtualization» more  VEE 2010»
14 years 4 months ago
AASH: an asymmetry-aware scheduler for hypervisors
Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs...
Vahid Kazempour, Ali Kamali, Alexandra Fedorova
FCCM
2011
IEEE
241views VLSI» more  FCCM 2011»
13 years 26 days ago
Multilevel Granularity Parallelism Synthesis on FPGAs
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
Alexandros Papakonstantinou, Yun Liang, John A. St...
CLUSTER
2007
IEEE
14 years 1 months ago
Efficient asynchronous memory copy operations on multi-core systems and I/OAT
Bulk memory copies incur large overheads such as CPU stalling (i.e., no overlap of computation with memory copy operation), small register-size data movement, cache pollution, etc...
Karthikeyan Vaidyanathan, Lei Chai, Wei Huang, Dha...
ADHOC
2008
103views more  ADHOC 2008»
13 years 9 months ago
Impact of sensor-enhanced mobility prediction on the design of energy-efficient localization
Energy efficiency and positional accuracy are often contradictive goals. We propose to decrease power consumption without sacrificing significant accuracy by developing an energy-...
Chuang-Wen You, Polly Huang, Hao-Hua Chu, Yi-Chao ...
ICDE
2003
IEEE
141views Database» more  ICDE 2003»
14 years 10 months ago
HDoV-tree: The Structure, The Storage, The Speed
In a visualization system, one of the key issues is to optimize performance and visual fidelity. This is especially critical for large virtual environments where the models do not...
Lidan Shou, Zhiyong Huang, Kian-Lee Tan