AASH: an asymmetry-aware scheduler for hypervisors

Asymmetric multicore processors (AMP) consist of cores exposing the same instruction-set architecture (ISA) but varying in size, frequency, power consumption and performance. AMPs were shown to be more power efficient than conventional symmetric multicore processors, and it is therefore likely that future multicore systems will include cores of different types. AMPs derive their efficiency from core specialization: instruction streams can be assigned to run on the cores best suited to their demands for architectural resources. System efficiency is improved as a result. To perform effective matching of threads to cores, the thread scheduler must be asymmetry-aware; and while asymmetry-aware schedulers for operating systems are a well studied topic, asymmetry-awareness in hypervisors has not been addressed. A hypervisor must be asymmetry-aware to enable proper functioning of asymmetryaware guest operating systems; otherwise they will be ineffective in virtual environments. Furthermor...

• Type: Conference
• Year: 2010
• Where: VEE
• Authors: Vahid Kazempour, Ali Kamali, Alexandra Fedorova
• Keywords: Cores, Hypervisor, Multicore Processors, VEE 2010, Virtualization