1040 search results - page 6 / 208 » A Comparative Performance Evaluation of Write Barrier Implem... |
ISCA
2006
IEEE
13 years 7 months ago
2006
IEEE
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
SYSTOR
2009
ACM
14 years 2 months ago
2009
ACM
Data compression has been claimed to be an attractive solution to save energy consumption in high-end servers and data centers. However, there has not been a study to explore this...
HPCA
1996
IEEE
13 years 12 months ago
1996
IEEE
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...
ICPPW
2005
IEEE
14 years 1 months ago
2005
IEEE
Large–scale parallel applications performing global synchronization may spend a significant amount of execution time waiting for the completion of a barrier operation. Conseque...
SPAA
2009
ACM
14 years 4 months ago
2009
ACM
In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is...