ISCA 2006 - PDF Preprint Papers

ISCA 2006 International Symposium on Computer Architecture

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ISCA
2006
IEEE

187views Hardware» more ISCA 2006»

A Case for MLP-Aware Cache Replacement

14 years 5 months ago

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Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...

Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...

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Id	Views	Title	Status

1	187	A Case for MLP-Aware Cache Replacement	claim
2	182	Cooperative Caching for Chip Multiprocessors	claim
3	169	Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches	claim
4	164	Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture	claim
5	162	Design and Management of 3D Chip Multiprocessors Using Network-in-Memory	claim
6	158	Memory Model = Instruction Reordering + Store Atomicity	claim
7	154	SODA: A Low-power Architecture For Software Radio	claim
8	154	An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors	claim
9	151	The BlackWidow High-Radix Clos Network	claim
10	150	Spatial Memory Streaming	claim
11	148	Tolerating Dependences Between Large Speculative Threads Via Sub-Threads	claim
12	145	Techniques for Multicore Thermal Management: Classification and New Exploration	claim
13	144	Conditional Memory Ordering	claim
14	142	Bulk Disambiguation of Speculative Threads in Multiprocessors	claim
15	138	Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs	claim
16	138	Learning-Based SMT Processor Resource Distribution via Hill-Climbing	claim
17	138	The Future of Virtualization Technology	claim
18	137	Interconnect-Aware Coherence Protocols for Chip Multiprocessors	claim
19	137	Multiple Instruction Stream Processor	claim
20	133	TRAP-Array: A Disk Array Architecture Providing Timely Recovery to Any Point-in-time	claim
21	131	Reducing Startup Time in Co-Designed Virtual Machines	claim
22	130	Area-Performance Trade-offs in Tiled Dataflow Architectures	claim
23	125	Architectural Semantics for Practical Transactional Memory	claim
24	123	Improving Cost, Performance, and Security of Memory Encryption and Authentication	claim
25	123	A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks	claim
26	121	Flexible Snooping: Adaptive Forwarding and Filtering of Snoops in Embedded-Ring Multiprocessors	claim
27	120	Interconnection Networks for Scalable Quantum Computers	claim
28	114	Ensemble-level Power Management for Dense Blade Servers	claim
29	114	Using System-on-a-Programmable-Chip Technology to Design Embedded Systems	claim
30	108	Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification	claim
31	107	Distributed Arithmetic on a Quantum Multicomputer	claim
32	92	Quantum Memory Hierarchies: Efficient Designs to Match Available Parallelism in Quantum Computing	claim

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