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ISSS
2002
IEEE
141views Hardware» more  ISSS 2002»
14 years 25 days ago
An Accelerated Datapath Width Optimization Scheme for Area Reduction of Embedded Systems
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and r...
Hiroto Yasuura, Yun Cao, Mohammad Mesbah Uddin
BCS
2008
13 years 9 months ago
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation
This paper describes our approaches to raise the level of abstraction at which hardware suitable for accelerating computationally-intensive applications can be specified. Field-Pr...
Qiang Liu, George A. Constantinides, Konstantinos ...
EUROPAR
2005
Springer
14 years 1 months ago
SPC-XML: A Structured Representation for Nested-Parallel Programming Languages
Nested-parallelism programming models, where the task graph associated to a computation is series-parallel, present good analysis properties that can be exploited for scheduling, c...
Arturo González-Escribano, Arjan J. C. van ...
ICFEM
2009
Springer
13 years 5 months ago
Implementing a Direct Method for Certificate Translation
Abstract. Certificate translation is a method that transforms certificates of source programs into certificates of their compilation. It provides strong guarantees on low-level cod...
Gilles Barthe, Benjamin Grégoire, Sylvain H...
TC
2010
13 years 2 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch