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» A Complete Multi-valued SAT Solver
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ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
13 years 11 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...
IPPS
2009
IEEE
14 years 2 months ago
Combining multiple heuristics on discrete resources
—In this work we study the portfolio problem which is to find a good combination of multiple heuristics to solve given instances on parallel resources in minimum time. The resou...
Marin Bougeret, Pierre-François Dutot, Alfr...
ATVA
2007
Springer
108views Hardware» more  ATVA 2007»
14 years 1 months ago
A New Approach to Bounded Model Checking for Branching Time Logics
Abstract. Bounded model checking (BMC) is a technique for overcoming the state explosion problem which has gained wide industrial acceptance. Bounded model checking is typically ap...
Rotem Oshman, Orna Grumberg
FROCOS
2005
Springer
14 years 1 months ago
Combination of Isabelle/HOL with Automatic Tools
We describe results and status of a sub project of the Verisoft [1] project. While the Verisoft project aims at verification of a complete computer system starting with hardware a...
Sergey Tverdyshev
COMBINATORICS
2004
102views more  COMBINATORICS 2004»
13 years 7 months ago
Satisfiability and Computing van der Waerden Numbers
In this paper we bring together the areas of combinatorics and propositional satisfiability. Many combinatorial theorems establish, often constructively, the existence of positive...
Michael R. Dransfield, Lengning Liu, Victor W. Mar...