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ICSE
2003
IEEE-ACM
14 years 9 months ago
Architectural Level Risk Assessment Tool Based on UML Specifications
Recent evidences indicate that most faults in software systems are found in only a few of a system's components [1]. The early identification of these components allows an or...
T. Wang, Ahmed E. Hassan, Ajith Guedem, Walid Abde...
ICSM
2003
IEEE
14 years 2 months ago
Software Architecture Recovery based on Pattern Matching
This paper is a summary of the author’s thesis that presents a model and an environment for recovering the high level design of legacy software systems based on user defined ar...
Kamran Sartipi
IESS
2007
Springer
120views Hardware» more  IESS 2007»
14 years 3 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...
EMSOFT
2004
Springer
14 years 2 months ago
Heterogeneous reactive systems modeling: capturing causality and the correctness of loosely time-triggered architectures (LTTA)
We present an extension of a mathematical framework proposed by the authors to deal with the composition of heterogeneous reactive systems. Our extended framework encompasses dive...
Albert Benveniste, Benoît Caillaud, Luca P. ...
LCTRTS
2005
Springer
14 years 2 months ago
Complementing software pipelining with software thread integration
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...
Won So, Alexander G. Dean