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    IESS   2007 International Embedded Systems Symposium
    Wall of Fame | Most Viewed IESS-2007 Paper
    IESS
    2007
    Springer
    165views Hardware» more  IESS 2007»
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
    14 years 5 months ago
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
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    NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
    Ilya Issenin, Nikil Dutt
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    1Download preprint from source165
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
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    2Download preprint from source162
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs
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    3Download preprint from source158
    Dynamic Software Update of Resource-Constrained Distributed Embedded Systems
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    4Download preprint from source156
    Automatic Data Path Generation from C code for Custom Processors
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    5Download preprint from source143
    Embedded Software Development in a System-Level Design Flow
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    6Download preprint from source138
    Medical Embedded Systems
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    7Download preprint from source128
    An Interactive Design Environment for C-based High-Level Synthesis
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    8Download preprint from source124
    Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
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    9Download preprint from source120
    Error Containment in the Time-Triggered System-On-a-Chip Architecture
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    10Download preprint from source116
    Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
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    11Download preprint from source110
    Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
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    12Download preprint from source92
    An Interactive Model Re-Coder for Efficient SoC Specification
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