Sciweavers

    IESS   2007 International Embedded Systems Symposium
    Wall of Fame | Most Viewed IESS-2007 Paper
    IESS
    2007
    Springer
    165views Hardware» more  IESS 2007»
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
    14 years 6 months ago
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
    Download  www.ics.uci.edu
    NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a signific...
    Ilya Issenin, Nikil Dutt
    claim paper
    Read More »
    Disclaimer and Copyright Notice
    Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.
    IdReadViewsTitleStatus
    1Download preprint from source165
    Data Reuse Driven Memory and Network-On-Chip Co-Synthesis
    claim
    2Download preprint from source162
    Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs
    claim
    3Download preprint from source158
    Dynamic Software Update of Resource-Constrained Distributed Embedded Systems
    claim
    4Download preprint from source156
    Automatic Data Path Generation from C code for Custom Processors
    claim
    5Download preprint from source143
    Embedded Software Development in a System-Level Design Flow
    claim
    6Download preprint from source138
    Medical Embedded Systems
    claim
    7Download preprint from source128
    An Interactive Design Environment for C-based High-Level Synthesis
    claim
    8Download preprint from source124
    Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
    claim
    9Download preprint from source120
    Error Containment in the Time-Triggered System-On-a-Chip Architecture
    claim
    10Download preprint from source116
    Utilizing Reconfigurable Hardware to Optimize Workflows in Networked Nodes
    claim
    11Download preprint from source110
    Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
    claim
    12Download preprint from source92
    An Interactive Model Re-Coder for Efficient SoC Specification
    claim
    Explore & Download
    Proceedings Preprints Top 5 Ranked Papers Publications Books Software Tutorials Presentations Lectures Notes Datasets
    Productivity Tools
    International On-screen Keyboard Graphical Social Symbols OCR Text Recognition CSS3 Style Generator Web Page to PDF Web Page to Image PDF Split PDF Merge Latex Equation Editor Sci2ools
    Document Tools
    PDF to Text PDF to Postscript PDF to Thumbnails Excel to PDF Word to PDF Postscript to PDF PowerPoint to PDF Latex to Word Repair Corrupted PDF
    Image Tools
    JPG to PS JPG to PDF Extract Images from PDF Image Converter
    Sciweavers
    About Community Cookies Privacy Policy Terms of Use

    Copyright © Sciweavers LLC, 2009-2024, USA.