68 search results - page 6 / 14 » A Configuration Concept for a Massively Parallel FPGA Archit... |
ICDCS
1995
IEEE
13 years 11 months ago
1995
IEEE
MASSIVE is a distributed virtual reality system. It provides rich facilities to support user interaction and cooperation via text, audio and graphics media, and interaction is con...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
This paper presents a hardware architecture for face detection based system on AdaBoost algorithm using Haar features. We describe the hardware design techniques including image s...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
HPCA
2000
IEEE
13 years 12 months ago
2000
IEEE
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...