Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
We present FixIt(ALC), a novel procedure for deciding knowledge base (KB) satisfiability in the Fuzzy Description Logic (FDL) ALC. FixIt(ALC) does not search for tree-structured m...
We present a verified compiler to an idealized assembly language from a small, untyped functional language with mutable references and exceptions. The compiler is programmed in th...
We propose a lightweight approach for certification of Java bytecode monitor inlining using proof-carrying code. The main purpose of such a framework is to enable development use ...
Abstract. We present a method based on logic program transformation, for verifying Computation Tree Logic (CTL∗ ) properties of finite state reactive systems. The finite state ...
Alberto Pettorossi, Maurizio Proietti, Valerio Sen...