714 search results - page 12 / 143 » A Decompression Architecture for Low Power Embedded Systems |
CAL
2002
13 years 7 months ago
2002
RTAS
2000
IEEE
13 years 12 months ago
2000
IEEE
—Many embedded systems operate under severe power and energy constraints. Voltage clock scaling is one mechanism by which energy consumption may be reduced: It is based on the fa...
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. Dictionary-based code c...
ASYNC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...