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» A Decompression Architecture for Low Power Embedded Systems
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JCSC
2002
87views more  JCSC 2002»
13 years 8 months ago
Power Estimator Development for Embedded System Memory Tuning
Memory accesses account for a large percentage of total power in microprocessor-based embedded systems. The increasing use of microprocessor cores and synthesis, rather than prefa...
Frank Vahid, Tony Givargis, Susan Cotterell
HPCA
2000
IEEE
14 years 1 months ago
PowerMANNA: A Parallel Architecture Based on the PowerPC MPC620
The paper presents PowerMANNA - a distributed-memory parallel computer system based on the 64-Bit PowerPC processor MPC620. The PowerMANNA node architecture supports all the sophi...
Peter M. Behr, S. Pletner, Angela C. Sodan
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
14 years 1 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
ISLPED
1995
ACM
235views Hardware» more  ISLPED 1995»
14 years 8 days ago
Low power and EMI, high frequency, crystal oscillator
The high-frequency oscillator is one of the major causes of both high power consumption and high ElectroMagnetic Interference (EMI) in Embedded Systems (ES). This paper presents a...
Rafael Fried, Reuven Holzer
IPPS
2006
IEEE
14 years 2 months ago
A stochastic multi-objective algorithm for the design of high performance reconfigurable architectures
The increasing demand for FPGAs and reconfigurable hardware targeting high performance low power applications has lead to an increasing requirement for new high performance reconf...
Wing On Fung, Tughrul Arslan