59 search results - page 11 / 12 » A Delay Model and Speculative Architecture for Pipelined Rou... |
ISLPED
2005
ACM
14 years 20 days ago
2005
ACM
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
IDMS
2001
Springer
13 years 11 months ago
2001
Springer
A number of research studies show that the operating system has a substantial influence on communication delay in distributed environments. Thus, in order to provide applications w...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
INFOCOM
2007
IEEE
14 years 1 months ago
2007
IEEE
— The input-queued switch architecture is widely used in Internet routers due to its ability to run at very high line speeds. A central problem in designing an input-queued switc...
CN
2008
13 years 7 months ago
2008
Electrical-to-optical domain conversions and vice versa (denoted by O/E/O conversions) for each hop in optical core transport networks impose considerable capital and financial ov...