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» A Design System based on Architectural Representations
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SLIP
2006
ACM
15 years 10 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
JSA
2010
158views more  JSA 2010»
14 years 11 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
197
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WMCSA
2003
IEEE
15 years 9 months ago
Design and Evaluation of a Metropolitan Area Multitier Wireless Ad Hoc Network Architecture
Few real-world applications of mobile ad hoc networks have been developed or deployed outside the military environment, and no traces of actual node movement in a real ad hoc netw...
Jorjeta G. Jetcheva, Yih-Chun Hu, Santashil PalCha...
IISWC
2008
IEEE
15 years 10 months ago
Reproducible simulation of multi-threaded workloads for architecture design exploration
As multiprocessors become mainstream, techniques to address efficient simulation of multi-threaded workloads are needed. Multi-threaded simulation presents a new challenge: non-d...
Cristiano Pereira, Harish Patil, Brad Calder
EUROMICRO
1998
IEEE
15 years 8 months ago
Experiments with MHEG Player/Studio: An Interactive Hypermedia Visualization and Authoring System
With the growing needs of information sharing and exchange, MHEG-6(Multimedia Hypermedia information coding Expert Group - part 6) standard is defined so as to provide the interna...
Seungtaek Oh, Yung Yi, Seunghoon Jeong, Yanghee Ch...