162 search results - page 7 / 33 » A Distributed Cache Coherence Protocol for Hypercube Multipr... |
IPPS
1993
IEEE
14 years 16 days ago
1993
IEEE
DSD
2009
IEEE
14 years 8 days ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
CDES
2008
13 years 9 months ago
2008
Although directory-based cache coherence protocols are the best choice when designing chip multiprocessor architectures (CMPs) with tens of processor cores on chip, the memory ove...
HPCA
1999
IEEE
14 years 21 days ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
CHARME
2001
Springer
14 years 1 days ago
2001
Springer
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...