Sciweavers

238 search results - page 21 / 48
» A Distributed Control Path Architecture for VLIW Processors
Sort
View
IPPS
2005
IEEE
14 years 1 months ago
Control-Flow Independence Reuse via Dynamic Vectorization
Current processors exploit out-of-order execution and branch prediction to improve instruction level parallelism. When a branch prediction is wrong, processors flush the pipeline ...
Alex Pajuelo, Antonio González, Mateo Valer...
IEEEPACT
1999
IEEE
13 years 12 months ago
Predicated Static Single Assignment
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
Lori Carter, Beth Simon, Brad Calder, Larry Carter...
HPCA
2008
IEEE
14 years 8 months ago
DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors
Increases in peak current draw and reductions in the operating voltages of processors continue to amplify the importance of dealing with voltage fluctuations in processors. Noise-...
Meeta Sharma Gupta, Krishna K. Rangan, Michael D. ...
CF
2005
ACM
13 years 9 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
TRIDENTCOM
2006
IEEE
14 years 1 months ago
A testbed demonstrating optical IP switching (OIS) in disaggregated network architectures
: The lack of a unified control plane does not allow current optical networks to dynamically provision new optical paths. The IETF standardization body has proposed the Generalized...
Marco Ruffini, Donal O'Mahony, Linda Doyle