HPCA 2008 - PDF Preprint Papers

HPCA 2008 International Symposium on High-Performance Computer Architecture

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HPCA
2008
IEEE

250views Distributed And Parallel Com...» more HPCA 2008»

A comprehensive approach to DRAM power management

15 years 1 months ago

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This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...

Ibrahim Hur, Calvin Lin

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Id	Views	Title	Status

1	250	A comprehensive approach to DRAM power management	claim
2	198	Automated microprocessor stressmark generation	claim
3	196	System level analysis of fast, per-core DVFS using on-chip switching regulators	claim
4	196	Amdahl's Law in the multicore era	claim
5	194	Regional congestion awareness for load balance in networks-on-chip	claim
6	190	Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems	claim
7	182	C-Oracle: Predictive thermal management for data centers	claim
8	174	An OS-based alternative to full hardware coherence on tiled CMPs	claim
9	169	High-throughput pairwise point interactions in Anton, a specialized machine for molecular dynamics simulation	claim
10	166	DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors	claim
11	164	Performance and power optimization through data compression in Network-on-Chip architectures	claim
12	159	Thread-safe dynamic binary translation using transactional memory	claim
13	157	FlexiTaint: A programmable accelerator for dynamic taint propagation	claim
14	155	Cluster-level feedback power control for performance optimization	claim
15	154	EXCES: External caching in energy saving storage systems	claim
16	154	Fabric convergence implications on systems architecture	claim
17	154	Incorporating flexibility in Anton, a specialized machine for molecular dynamics simulation	claim
18	152	Speculative instruction validation for performance-reliability trade-off	claim
19	148	Supporting highly-decoupled thread-level redundancy for parallel programs	claim
20	148	Prediction of CPU idle-busy activity pattern	claim
21	146	Runtime validation of memory ordering using constraint graph checking	claim
22	138	Uncovering hidden loop level parallelism in sequential applications	claim
23	136	Serializing instructions in system-intensive workloads: Amdahl's Law strikes again	claim
24	134	Address-branch correlation: A novel locality for long-latency hard-to-predict branches	claim
25	132	Runahead Threads to improve SMT performance	claim
26	130	Single-level integrity and confidentiality protection for distributed shared memory multiprocessors	claim
27	122	CMP network-on-chip overlaid with multi-band RF-interconnect	claim
28	121	Performance-aware speculation control using wrong path usefulness prediction	claim
29	119	PEEP: Exploiting predictability of memory dependences in SMT processors	claim
30	119	Branch-mispredict level parallelism (BLP) for control independence	claim
31	118	Roughness of microarchitectural design topologies and its implications for optimization	claim
32	115	PaCo: Probability-based path confidence prediction	claim
33	105	Power-Efficient DRAM Speculation	claim
34	105	Fundamental performance constraints in horizontal fusion of in-order cores	claim
35	97	Design and implementation of the blue gene/P snoop filter	claim

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