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» A Distributed Control Path Architecture for VLIW Processors
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ICS
2007
Tsinghua U.
14 years 1 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
LCTRTS
2004
Springer
14 years 27 days ago
A trace-based binary compilation framework for energy-aware computing
Energy-aware compilers are becoming increasingly important for embedded systems due to the need to meet conflicting constraints on time, code size and power consumption. We intro...
Lian Li 0002, Jingling Xue
CONCURRENCY
2006
111views more  CONCURRENCY 2006»
13 years 7 months ago
ScyFlow: an environment for the visual specification and execution of scientific workflows
With the advent of grid technologies, scientists and engineers are building more and more complex applications to utilize distributed grid resources. The core grid services provid...
Karen M. McCann, Maurice Yarrow, Adrian De Vivo, P...
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
14 years 1 months ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh
HPCA
2005
IEEE
14 years 8 months ago
Tapping ZettaRAMTM for Low-Power Memory Systems
ZettaRAMTM is a new memory technology under development by ZettaCoreTM as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor...
Ravi K. Venkatesan, Ahmed S. Al-Zawawi, Eric Roten...